In June last year, TI has released details of 45-nanometer lifebook t4010 battery process technology, the process uses 193-nm immersion lithography, can each double the number of wafer output. Through the use of multiple technologies, TI will SoC processor performance increased by 30% and 40% while reducing power consumption. TI plans to start in 2007 to provide 45-nm wireless product samples, the first batch of products, production is scheduled for mid-2008. High-k dielectrics will be introduced to the follow-up 45-nanometer fujitsu t4210 battery process version, for TI's highest performance products.
Several 45-nm solution that not only meet our customers a unique end-product requirements fujitsu FPCBP155, but also for creating flexible, optimized design provides a wealth of options. These options include a low-power technology, which can extend battery life in portable products, while for the highly integrated SoC designs to provide adequate performance to support advanced multimedia features. Mid-range process supports TI DSP and high-performance ASIC library fujitsu t4220 battery , lifebook p1510 battery, can meet the demand for communications infrastructure products. In addition, as the first high-k materials, technology, highest performance 45-nanometer technology options also supports MPU-class performance ibm 92P1101.
